1. Field of the Invention
The present invention relates to atomic switching devices capable of providing extremely high integration density and extremely high speed operation, and logical circuits using such atomic switching devices. More particularly, the present invention relates to switching devices and logical circuits capable of providing extremely high integration density and extremely high speed operation, the high speed operation being realized by changing the conductance of an atom wire constituted by a plurality of atoms by moving a particular atom of the atom wire.
The present invention relates to ultra-fine electronics devices and logical circuits using such devices. More particularly, the present invention relates to an atom wire of an atomic level size having a plurality of atoms arranged in a line or in a plurality of lines, in a ring shape, or in a curved line, and relates to devices and logical circuits using such devices for switching an atom wire by the field effect of a gate made of an atom wire.
The present invention also relates to a method of configuring the uppermost surface structure of a substrate, of a device for switching an atom wire, or of a logical circuit using such a device. More particularly, the present invention relates to a method of configuring the surface structure of a substrate by controlling the positions of a plurality of atoms to be attached or removed by applying X-rays.
2. Description of the Related Art
The most typical one of conventional switching devices is a metal oxide semiconductor field effect transistor MOSFET. This device is constituted by a gate oxide film, gate, source, and drain formed on a silicon substrate. A channel is formed within the substrate in contact with the gate oxide film, and current flows between the source and drain. In a MOSFET, the conductance of the channel is controlled by a gate voltage.
The performance of a MOSFET is evaluated mainly by three factors: the level of voltage (threshold voltage) applied to the gate which is necessary for forming a channel, the channel conductance, and switching speed. The latter two factors are mainly determined by channel length, so that high performance has been dependent on a shorter gate length. The high performance of a MOSFET has been achieved heretofore depending in particular on a so-called scaling rule by which the size of a device is reduced three-dimensionally, i.e., height, width, and depth. Representing a proportional constant of device size reduction by k, the switching power consumption is proportional to k.sup.2 and the switching time is proportional to k. The device performance is therefore improved by reducing the device size.
However, reducing device size has limits. The minimum dimension is considered as 0.1 .mu.m at present in practical use. This limit is considered as being determined from a breakdown voltage of a p-n junction, a withstanding voltage of an insulating film, statistical variation of impurity concentrations, and wiring reliability. The depletion layer of a p-n junction is in the order of 20 nm to 30 nm, and the extension of the depletion layer when applying a voltage is in the order of 20 nm to 30 nm, totaling to about 0.1 .mu.m. If the thickness of an insulating film is 4 nm or thinner, current may flow by a tunnel phenomenon, so that the film will no longer adequately provide the function of serving as an insulating film.
Furthermore, in such a fine device, the amount of impurity material present in one impurity diffused region becomes 100 or less. Therefore, the statistical variation becomes in excess of 10%, substantially resulting in an inability to manufacture such devices. With the present device structure using a bulk effect, devices having a size of 0.1 .mu.m or smaller cannot be realized in practice.
Logical circuits using switching devices rely mainly upon the transistor switching characteristics, as in resistor-transistor logics (RTL), diode-transistor logics (DTL), and transistor-transistor logics (TTL). For example, in a TTL circuit made of MOS transistors, when a signal level "High" is applied to one of the gates of two MOS transistors, an output signal "Low" is obtained. If a signal level "Low" is applied to both the gates, an output signal "High" is obtained. This logical operation is called a NAND logical operation. A circuit having such a logical operation function is generally called a gate.
A TTL circuit is excellent in its stability relative to power supply voltage, noises and the like. It is therefore widely used in an integrated circuit. In this context, the more detailed description will be given. In a TTL circuit, if an input voltage is larger than a threshold voltage of a MOS transistor, an output is raised to a power supply voltage, and if smaller than the threshold voltage, an output is 0 V. The threshold voltage is generally near 1 V, and the power supply voltage is 5 V. Therefore, by using a TTL logical circuit, a voltage difference between "Low" and "High" can be boosted from 1 V up to 5 V. Even if the power supply voltage fluctuates more or less, the output level is sufficiently higher than the threshold voltage, ensuring a reliable operation. This TTL circuit is resistant against noises of a high level up to 1 V which is not realistic in an ordinary state.
Such a TTL circuit is constructed of transistors so that the integration density is determined by work dimension of transistors. As described previously, a conventional semiconductor technique has a limit in reducing the size of transistors because of physical limits concerning depletion layer extension of p-n junctions, statistical errors, and the like. Furthermore, a conventional switching device is required to flow a predetermined amount of current in order to switch it, and a large amount of current in order to switch it at high speed. The larger the current, the more the power is consumed, raising the temperature of the device. It is common for a recent large scale integrated circuit to integrate one million gates per square cm. The power consumption per one gate is required to be suppress to one hundred-thousands-th watt or less, because of a cooling limit.
There is a limit in integration density and switching speed so long as conventional switching devices are used.
The surface structure of a substrate on which a large scale integrated circuit using switching devices is formed, has been configured by using a photolithography method. This photolithography method uses masks and is not suitable for configuring the surface structure at an atomic level, because there are limits in mask work precision and exposure ultraviolet wavelength.